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innovative power tm - 1 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. act8848 advanced pmu for multi-core application processors features integrated power supplies ? four dc/dc step-down (buck) regulators ? 2 x 2.8a, 2 x 1.5a ? five low-noise ldos (350ma) ? three low-input voltage ldos (350ma) ? one low iq keep-alive ldo ? backup battery charger system control and interface ? six general purpose i/o with pwm drivers ? i 2 c serial interface ? interrupt controller system management ? reset interface and sequencing controller ? power on reset ? soft / hard reset ? watchdog supervision ? multiple sleep modes ? thermal management subsystem applications ? tablet pc ? mobile internet devices (mid) ? ebooks ? personal navigation devices general description the act8848 is a complete, cost effective, and highly-efficient activepmu tm power management solution optimized for the power, voltage sequencing and control requirements of telechips tcc88xx and samsung s5pc210 application processors. (please see the ordering information section to get the full part numbers.) the act8848 features four fixed-frequency, current-mode, synchronous pwm step-down converters that achieve peak efficiencies of up to 97%. these regulators operate with a fixed frequency of 2.25mhz, minimizing noise in sensitive applications and allowing the use of small external components. these buck regulators supply up to 2.8a of output current and can fully satisfy the power and control requirements of the multi-core application processors. dynamic voltage scaling (dvs) is supported either by dedicated control pins, or through i2c interface to optimize the energy-per- task performance for the processors. this device also includes eight low-noise ldos (up to 350ma per ldo), one always-on ldo and an integrated backup battery charger to provide the complete power system for the processors. the power sequence and reset controller provides power-on reset, sw-initiated reset, and power cycle reset for the processor. it also features the watchdog supervisory function. multiple sleep modes with autonomous sleep and wake-up sequence control are supported. the thermal management and protection subsystem allows the host processor to manage the power dissipation of the pmu and the overall system dynamically. the pmu provides a thermal warning to the host processor when the temperature reaches a certain threshold such that the system can turn off some of the non-essential functions, reduce the cl ock frequency and etc to manage the system temperature. the act8848 is available in a compact, pb-free and rohs-compliant tqfn66-48 package. rev 2, 15-nov-12
act8848 rev 2, 15-nov-12 innovative power tm - 2 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. table of contents general info rmation ........................................................................................................... .......................... p. 01 functional block diagram ...................................................................................................... ...................... p. 03 ordering in formation .......................................................................................................... .......................... p. 04 pin config uration ............................................................................................................. ............................ p. 04 pin descrip tions .............................................................................................................. ............................. p. 05 absolute maxi mum ratings ...................................................................................................... ................... p. 07 i 2 c interface electrical characteristics ........................................................................................ ................ p. 08 global regist er map ........................................................................................................... ......................... p. 09 register and bit descriptions ................................................................................................. ..................... p. 11 system control electric al characteristics ..................................................................................... ............... p. 16 step-down dc/dc electric al characteristics .................................................................................... .......... p. 17 low-noise ldo electric al characteristics ...................................................................................... ............. p. 18 low-input voltage ldo electr ical charac teristics .............................................................................. ......... p. 19 low-power (always-on) ldo el ectrical characteristics .......................................................................... ... p. 20 pwm led driver electric al characteristics ..................................................................................... ............ p. 20 typical performance characteristics?????????????????????????????..p. 21 system control information .................................................................................................... ..................... p. 26 interfacing with the telechip s tcc88xx proces sors ....................................................................... p. 26 control si gnals ............................................................................................................... .................. p. 27 push-button control ........................................................................................................... .............. p. 28 control s equences ............................................................................................................. .............. p. 28 watch-dog s upervisi on ......................................................................................................... .......... p. 28 software-initiat ed power cycle ................................................................................................ ........ p. 28 functional de scription ........................................................................................................ ......................... p. 30 i 2 c interf ace ................................................................................................................... .................. p. 30 housekeeping functions ........................................................................................................ .......... p. 30 thermal prot ection ............................................................................................................ ............... p. 30 step-down dc/d c regulators .................................................................................................... ................ p. 31 general description .......................................................................................................................... p. 3 1 100% duty cycl e operat ion ..................................................................................................... ........ p. 31 operating mode ............................................................................................................................... . p. 31 synchronous re ctification ..................................................................................................... ........... p. 31 soft-start .................................................................................................................... ...................... p. 31 compensation .................................................................................................................. ................ p. 31 configuration options ....................................................................................................................... p. 31 ok[ ] and output f ault interrupt .............................................................................................. ......... p. 32 pcb layout cons iderations ..................................................................................................... ........ p. 32 low-noise, low-dropout linear regulators ................................................................................................ p. 33 general description .......................................................................................................................... p. 3 3 output curr ent limit .......................................................................................................... ............... p. 33 compensation .................................................................................................................. ................ p. 33 configuration options ....................................................................................................................... p. 33 ok[ ] and output f ault interrupt .............................................................................................. ......... p. 33 pcb layout cons iderations ..................................................................................................... ........ p. 33 always-on ld o (reg13) ......................................................................................................... ................... p. 34 general description .......................................................................................................................... p. 3 4 reverse-current protection .................................................................................................... ......... p. 34 typical application ........................................................................................................... ................ p. 34 pwm led dr ivers ............................................................................................................... ......................... p. 35 pwm frequency selection ....................................................................................................... ........ p. 35 pwm duty cycl e select ion ...................................................................................................... ........ p. 35 tqfn66-48 package out line and dime nsions ...................................................................................... ..... p. 36
act8848 rev 2, 15-nov-12 innovative power tm - 3 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. functional block diagram
act8848 rev 2, 15-nov-12 innovative power tm - 4 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. pin configuration top view thin - qfn (tqfn66-48) ordering information c c : all active-semi components are rohs compliant and with pb-free plating unless specified differently. the term pb-free means semiconductor products that are in compliance with current rohs (restriction of hazardous substances) standards. 2 : act8848qm144-t has the same specification as act8848qm135-t except v out1 which is set as 1.5v to support ddr iii application. 3 : act8848 data sheet is described according to act8848qm135-t application; please see the appendix of ACT8848QM201-T for its specification. part number v out1 v out2 v out3 v out4 v out5 v out6 v out7 v out8 v out9 v out10 v out11 v out12 v out13 act8848qm135-t 1.8v 1.45v 1.25v 3.3v 2.8v 3.3v 3.3v 1.8v 1.2v 1.2v 1.8v 1.8v 3.3v ACT8848QM201-T 1.2v 1.2v 1.1v 1.1v 1.1v 1.1v 2.8v 1.8v 3.3v 1.2v 1.1v 1.8v 1.8v act8848qm144-t 1.5v 1.45v 1.25v 3.3v 2.8v 3.3v 3.3v 1.8v 1.2v 1.2v 1.8v 1.8v 3.3v package pins temperature range tqfn66-48 48 -40c to +85c act8848q m_ _ _ -t option code pin count package code product number active-semi tape and reel
act8848 rev 2, 15-nov-12 innovative power tm - 5 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. pin descriptions pin name description 1, 2 sw3 switch node for reg3. 3 gp3 power ground for reg3. connect gp14, gp2, gp3, and ga together at a single point as close to the ic as possible. 4 out10 reg10 output. bypass it to ground with a 2.2f capacitor. 5 out11 reg11 output. bypass it to ground with a 2.2f capacitor. 6 inl3 power input for reg10, reg11 and reg12. 7 out12 reg12 output. bypass it to ground with a 2.2f capacitor. 8 vselr2 output voltage selection for reg2. drive to logic low to select default output voltage. drive to logic high to select secondary output voltage. 9 npbstat active-low open-drain push-button stat us output. npbstat is asserted low whenever the npbin is pushed, and is high-z otherwise. 10 gp2 power ground for reg2. connect gp14, gp 2, gp3, and ga together at a single point as close to the ic as possible. 11, 12 sw2 switch node for reg2. 13, 14 vp2 power input for reg2. bypass to gp2 with a high quality ceramic capacitor placed as close to the ic as possible. 15 out2 output voltage sense for reg2. 16 pwren power enable input. 17 refbp reference bypass. connect a 0.047 f ceramic capacitor from refbp to ga. this pin is discharged to ga in shutdown. 18 inl2 power input for reg8, reg9. 19 out9 reg9 output. bypass it to ground with a 2.2f capacitor. 20 ga analog ground. 21 out4 output voltage sense for reg4. 22 out8 reg8 output. bypass it to ground with a 2.2f capacitor. 23 sda data input for i 2 c serial interface. data is read on the rising edge of scl. 24 scl clock input for i 2 c serial interface. 25 vp4 power input for reg4. bypass to gp14 with a high quality ceramic capacitor placed as close to the ic as possible.
act8848 rev 2, 15-nov-12 innovative power tm - 6 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. pin descriptions cont?d pin name description 26 sw4 switch node for reg4. 27 gp14 power ground for reg1 and reg4. connect gp14, gp2, gp3, and ga together at a single point as close to the ic as possible. 28 sw1 switch node for reg1. 29 out1 output voltage sense for reg1. 30 vp1 power input for reg1. bypass to gp14 with a high quality ceramic capacitor placed as close to the ic as possible. 31 npbin master enable input. drive npbin to ga through a 50k ? resistor to enable the ic, drive npbin directly to ga to assert a manual-reset condition. 32 pwrhld power hold input. 33 nrsto open-drain reset output. 34 nirq open-drain interrupt output. 35 gpio6 general purpose i/o #6. configured as pwm le d driver output for up to 6ma current with programmable frequency and duty cycle. see the pwm led drive section for more information. 36 gpio5 general purpose i/o #5. configured as pwm le d driver output for up to 6ma current with programmable frequency and duty cycle. see the pwm led driver section for more information. 37 out13 reg13 output. bypass it to ground with a 2.2f capacitor. 38 out7 reg7 output. bypass it to ground with a 2.2f capacitor. 39 gpio4 general purpose i/o #4. configured as pwm le d driver output for up to 6ma current with programmable frequency and duty cycle. see the pwm led driver section for more information. 40 out6 reg6 output. bypass it to ground with a 2.2f capacitor. 41 inl1 power input for reg5, reg6, reg7. 42 out5 reg5 output. bypass it to ground with a 2.2f capacitor. 43 gpio3 general purpose i/o #3. configured as pwm le d driver output for up to 6ma current with programmable frequency and duty cycle. see the pwm led drier section for more information. 44 gpio2 general purpose i/o #2. configured as vselr4 for voltage selection of reg4. drive to logic low to select default output voltage. drive to logic high to select secondary output voltage. 45 gpio1 general purpose i/o #1. configured as vselr 3 for voltage selection of reg3. drive to logic low to select default output voltage. drive to logic high to select secondary output voltage. 46 out3 output voltage sense for reg3. 47,48 vp3 power input for reg3. bypass to gp3 with a high quality ceramic capacitor placed as close to the ic as possible. ep ep exposed pad. must be soldered to ground on pcb.
act8848 rev 2, 15-nov-12 innovative power tm - 7 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. absolute maximum ratings c parameter value unit inl1, inl2, inl3 to ga; vp1, sw1, out1 to gp14; vp2, sw2, out2 to gp2; vp3, sw3, out3 to gp3; vp4, sw4, out4 to gp14 -0.3 to 6 v gp14, gp2, gp3 to ga -0.3 to + 0.3 v out10, out11, out12 to ga -0.3 to inl3 + 0.3 v junction to ambien t thermal resistance 21 c/w operating ambient temperature range -40 to 85 c operating junction temperature -40 to 125 c storage temperature -55 to 150 c lead temperature (soldering, 10 sec) 300 c out8, out9, gpio1, gpio2, gpio3, gp io4, gpio5, gpio6, vselr2, npbin, nrsto, nirq, npbstat, pwren, pw rhld, refbp, scl, sda to ga -0.3 to inl2 + 0.3 v out5, out6, out7, out13 to ga -0.3 to inl1 + 0.3 v c : do not exceed these limits to prevent damage to the device. exposure to absolute maximum rati ng conditions for long periods m ay affect device reliability.
act8848 rev 2, 15-nov-12 innovative power tm - 8 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. figure 1: i 2 c compatible serial bus timing (v inl2 = 3.6v, t a = 25c, unless otherwise specified.) i 2 c interface electrical characteristics sda scl t st t su t hd t sp t scl start condition stop condition parameter test conditions min typ max unit scl, sda input low v inl2 = 3.1v to 5.5v, t a = -40oc to 85oc 0.35 v scl, sda input high v inl2 = 3.1v to 5.5v, t a = -40oc to 85oc 1.55 v sda leakage current 1 a sda output low i ol = 5ma 0.35 v scl clock period, t scl 1.5 s sda data setup time, t su 100 ns sda data hold time, t hd 300 ns start setup time, t st for start condition 100 ns stop setup time, t sp for stop condition 100 ns scl leakage current 1 a
act8848 rev 2, 15-nov-12 innovative power tm - 9 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. block address bits d7 d6 d5 d4 d3 d2 d1 d0 sys 0x00 name nbatlevmsk nbatstat vbatdat reserved batlev[3] batlev[2] batlev[1] batlev[0] default c 0 r r 0 0 0 0 0 sys 0x01 name ntmsk tstat reserved reserved reserved reserved reserved reserved default c 0 r 0 0 0 0 0 0 reg1 0x10 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default c 0 0 1 0 0 1 0 0 reg1 0x12 name on reserved reserved reserved reserved phase nfltmsk ok default c 1 1 0 0 0 0 0 r reg2 0x20 name reserved reserved vset0[5] vset0[4] vset0[3] vset0[2] vset0[1] vset0[0] default c 0 0 0 1 1 1 0 1 reg2 0x21 name reserved reserved vset1[5] vset1[4] vset1[3] vset1[2] vset1[1] vset1[0] default c 0 0 0 1 1 1 0 1 reg2 0x22 name on reserved reserved reserved reserved phase nfltmsk ok default c 1 1 0 0 0 0 0 r reg3 0x30 name reserved reserved vset0[5] vset0[4] vset0[3] vset0[2] vset0[1] vset0[0] default c 0 0 0 1 1 0 0 1 reg3 0x31 name reserved reserved vset1[5] vset1[4] vset1[3] vset1[2] vset1[1] vset1[0] default c 0 0 0 1 1 0 0 1 reg3 0x32 name on reserved reserved reserved reserved phase nfltmsk ok default c 1 1 0 0 0 1 0 r reg4 0x40 name reserved reserved vset0[5] vset0[4] vset0[3] vset0[2] vset0[1] vset0[0] default c 0 0 1 1 1 0 0 1 reg4 0x41 name reserved reserved vset1[5] vset1[4] vset1[3] vset1[2] vset1[1] vset1[0] default c 0 0 1 1 1 0 0 1 reg4 0x42 name on reserved reserved reserved reserved phase nfltmsk ok default c 1 1 0 0 0 1 0 r reg5 0x50 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default c 0 1 1 1 0 1 0 0 reg5 0x51 name on reserved reserved reserved reserved dis nfltmsk ok default c 1 1 0 0 0 1 0 r reg6 0x58 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default c 0 1 1 1 1 0 0 1 reg6 0x59 name on reserved reserved reserved reserved dis nfltmsk ok default c 1 1 0 0 0 1 0 r reg7 0x60 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default c 0 0 1 1 1 0 0 1 reg7 0x61 name on reserved reserved reserved reserved dis nfltmsk ok default c 0 0 0 0 0 1 0 r reg8 0x68 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default c 0 0 1 0 0 1 0 0 reg8 0x69 name on reserved reserved reserved reserved dis nfltmsk ok default c 0 0 0 0 0 1 0 r global register map c : default values of act8848qm135-t.
act8848 rev 2, 15-nov-12 innovative power tm - 10 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. block address bits d7 d6 d5 d4 d3 d2 d1 d0 reg9 0x70 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default c 0 0 0 1 1 0 0 0 reg9 0x71 name on reserved reserved reserved reserved dis nfltmsk ok default c 0 0 0 0 0 1 0 r reg10 0x80 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default c 0 1 0 1 1 0 0 0 reg10 0x81 name on reserved reserved reserved reserved dis nfltmsk ok default c 1 1 0 0 0 1 0 r reg11 0x90 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default c 0 0 1 0 0 1 0 0 reg11 0x91 name on reserved reserved reserved reserved dis nfltmsk ok default c 1 1 0 0 0 1 0 r reg12 0xa0 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default c 0 1 1 0 0 1 0 0 reg12 0xa1 name on reserved reserved reserved reserved dis nfltmsk ok default c 1 1 0 0 0 1 0 r reg13 0xb1 name on reserved reserved reserved reserved reserved reserved reserved default c 1 0 0 0 0 0 0 0 pb 0xc0 name pbamsk pbdmsk reserved reserved reserved reserved wdsren wdpcen default c 0 0 0 0 0 0 0 0 pb 0xc1 name intadr [7] intadr [6] intadr [5] intadr [4] intadr [3] intadr [2] intadr [1] intadr [0] default c r r r r r r r r pb 0xc2 name pbastat pbdstat pbdat reserved reserved reserved reserved reserved default c r r r r r r r r pb 0xc3 name reserved reserved reserved reserved reserved reserved reserved sipc default c 0 0 0 0 0 0 0 0 pb 0xc5 name reserved reserved reserved reserved reserved reserved pcstat srstat default c 0 0 0 0 0 0 r r gpio6 0xe3 name pwm6en fre6[2] fre6[1] fre6[0] duty6[3] duty6[2] duty6[1] duty6[0] default c 0 0 0 0 0 0 0 0 gpio5 0xe4 name pwm5en fre5[2] fre5[1] fre5[0] duty5[3] duty5[2] duty5[1] duty5[0] default c 0 0 0 0 0 0 0 0 gpio3 0xf4 name pwm3en fre3[2] fre3[1] fre3[0] duty3[3] duty3[2] duty3[1] duty3[0] default c 0 0 0 0 0 0 0 0 gpio4 name pwm4en fre4[2] fre4[1] fre4[0] duty4[3] duty4[2] duty4[1] duty4[0] default c 0 0 0 0 0 0 0 0 0xf5 global register map cont?d c : default values of act8848qm135-t.
act8848 rev 2, 15-nov-12 innovative power tm - 11 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. register and bit descriptions block address bit name access description sys 0x00 [7] nbatlevmsk r/w battery voltage level interrupt ma sk. set this bit to 1 to unmask the interrupt. see the programmable battery voltage monitor section for more information sys 0x00 [6] nbatstat r battery voltage status. value is 1 when batlev interrupt is generated, value is 0 otherwise. sys 0x00 [5] vbatdat r battery voltage monitor real time status. value is 1 when vbat < batlev, value is 0 otherwise. sys 0x00 [4] - r/w reserved. sys 0x00 [3:0] batlev r/w battery voltage detect threshold. defines the batlev voltage threshold. see the programmable battary voltage monitor section for more information. sys 0x01 [7] ntmsk r/w thermal interrupt mask. set this bit to 1 to unmask the interrupt. sys 0x01 [6] tstat r thermal interrupt status. value is 1 when a thermal interrupt is generated, value is 0 otherwise. sys 0x01 [5:0] - r/w reserved. reg1 0x10 [5:0] vset0 r/w primary output voltage selection. see the output voltage programming section for more information reg1 0x12 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg1 0x12 [6:3] - r reserved. reg1 0x12 [2] phase r/w regulator phase control. set bit to 1 for the regulator to operate 180 out of phase with the oscillator, clear bit to 0 for the regulator to operate in phase with the oscillator. reg1 0x12 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault-interrupts, clear bit to 0 to disa ble fault-interrupts. reg1 0x12 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg2 0x20 [7:6] - r reserved. reg2 0x20 [5:0] vset0 r/w primary output voltage selection. valid when vsel is driven low. see the output voltage programming section for more information reg2 0x21 [7:6] - r reserved. reg2 0x21 [5:0] vset1 r/w secondary output voltage selection. valid when vsel is driven high. see the output voltage programming section for more information. reg2 0x22 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg2 0x22 [6:3] - r reserved. reg2 0x22 [2] phase r/w regulator phase control. set bit to 1 for the regulator to operate 180 out of phase with the oscillator, clear bit to 0 for the regulator to operate in phase with the oscillator. reg2 0x22 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault-interrupts, clear bit to 0 to disa ble fault-interrupts. reg2 0x22 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg3 0x30 [7:6] - r reserved. reg3 0x30 [5:0] vset0 r/w primary output voltage selection. valid when vsel is driven low. see the output voltage programming section for more information reg3 0x31 [7:6] - r reserved. reg1 0x10 [7:6] - r reserved.
act8848 rev 2, 15-nov-12 innovative power tm - 12 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. register and bit descriptions cont?d block address bit name access description reg3 0x31 [5:0] vset1 r/w secondary output voltage selection. valid when vsel is driven high. see the output voltage programming section for more information. reg3 0x32 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg3 0x32 [6:3] - r reserved. reg3 0x32 [2] phase r/w regulator phase control. set bit to 1 for the regulator to operate 180 out of phase with the oscillator, clear bit to 0 for the regulator to operate in phase with the oscillator. reg3 0x32 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault-interrupts, clear bit to 0 to disa ble fault-interrupts. reg3 0x32 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg4 0x40 [7:6] - r reserved. reg4 0x40 [5:0] vset0 r/w primary output voltage selection. valid when vsel is driven low. see the output voltage programming section for more information reg4 0x41 [7:6] - r reserved. reg4 0x41 [5:0] vset1 r/w secondary output voltage selection. valid when vsel is driven high. see the output voltage programming section for more information. reg4 0x42 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg4 0x42 [6:3] - r reserved. reg4 0x42 [2] phase r/w regulator phase control. set bit to 1 for the regulator to operate 180 out of phase with the oscillator, clear bit to 0 for the regulator to operate in phase with the oscillator. reg4 0x42 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault-interrupts, clear bit to 0 to disa ble fault-interrupts. reg4 0x42 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg5 0x50 [7:6] - r reserved. reg5 0x50 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg5 0x51 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg5 0x51 [6:3] - r reserved. reg5 0x51 [2] dis r/w output discharge control. w hen activated, ldo output is discharged to ga through 1.5k ? resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg5 0x51 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault-interrupts, clear bit to 0 to disa ble fault-interrupts. reg5 0x51 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg6 0x58 [7:6] - r reserved. reg6 0x58 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg6 0x59 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg6 0x59 [6:3] - r reserved.
act8848 rev 2, 15-nov-12 innovative power tm - 13 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. register and bit descriptions cont?d block address bit name access description reg6 0x59 [2] dis r/w output discharge control. w hen activated, ldo output is discharged to ga through 1.5k ? resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg6 0x59 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault-interrupts, clear bit to 0 to disa ble fault-interrupts. reg6 0x59 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg7 0x60 [7:6] - r reserved. reg7 0x60 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg7 0x61 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg7 0x61 [6:3] - r reserved. reg7 0x61 [2] dis r/w output discharge control. w hen activated, ldo output is discharged to ga through 1.5k ? resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg7 0x61 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault-interrupts, clear bit to 0 to disa ble fault-interrupts. reg7 0x61 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg8 0x68 [7:6] - r reserved. reg8 0x68 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg8 0x69 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg8 0x69 [6:3] - r reserved. reg8 0x69 [2] dis r/w output discharge control. w hen activated, ldo output is discharged to ga through 1.5k ? resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg8 0x69 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault-interrupts, clear bit to 0 to disa ble fault-interrupts. reg8 0x69 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg9 0x70 [7:6] - r reserved. reg9 0x70 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg9 0x71 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg9 0x71 [6:3] - r reserved. reg9 0x71 [2] dis r/w output discharge control. w hen activated, ldo output is discharged to ga through 1.5k ? resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg9 0x71 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault-interrupts, clear bit to 0 to disa ble fault-interrupts. reg9 0x71 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg10 0x80 [7:6] - r reserved.
act8848 rev 2, 15-nov-12 innovative power tm - 14 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. register and bit descriptions cont?d block address bit name access description reg10 0x80 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg10 0x81 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg10 0x81 [6:3] - r reserved. reg10 0x81 [2] dis r/w output discharge control. w hen activated, ldo output is discharged to ga through 1.5k ? resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg10 0x81 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault-interrupts, clear bit to 0 to disa ble fault-interrupts. reg10 0x81 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg11 0x90 [7:6] - r reserved. reg11 0x90 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg11 0x91 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg11 0x91 [6:3] - r reserved. reg11 0x91 [2] dis r/w output discharge control. w hen activated, ldo output is discharged to ga through 1.5k ? resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg11 0x91 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault-interrupts, clear bit to 0 to disa ble fault-interrupts. reg11 0x91 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg12 0xa0 [7:6] - r reserved. reg12 0xa0 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg12 0xa1 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg12 0xa1 [6:3] - r reserved. reg12 0xa1 [2] dis r/w output discharge control. w hen activated, ldo output is discharged to ga through 1.5k ? resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg12 0xa1 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault-interrupts, clear bit to 0 to disa ble fault-interrupts. reg12 0xa1 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg13 0xb1 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg13 0xb1 [6:0] - r reserved. pb 0xc0 7 npbamsk r/w npbin assertion interrupt control. set this bit to 1 to generate an interrupt when npbin is asserted. pb 0xc0 6 npbdmsk r/w npbin de-assertion interrupt cont rol. set this bit to 1 to generate an interrupt wh en npbin is de-asserted. pb 0xc0 [5:2] - r reserved.
act8848 rev 2, 15-nov-12 innovative power tm - 15 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. register and bit descriptions cont?d block address bit name access description pb 0xc0 1 wdsren r/w watchdog soft-reset enable. set this bit to 1 to enable watchdog function. when the watchdog timer expires, the pmu commences a soft-reset routine. this bit is automatically reset to 0 when entering sleep mode. pb 0xc0 0 wdpcen r/w watchdog power-cycle enable. set this bit to 1 to enable watchdog function. when watchdog timer expires, the pmu commence a power cycle. this bit is automatically reset to 0 when entering sleep mode. pb 0xc1 [7:0] intadr r interrupt address. it holds the addr ess of the block that triggers the interrupt. this byte defaults to 0xff and is automatically set to 0xff after being read. bit 7 is the msb while bit 0 is the lsb. pb 0xc2 7 pbastat r npbin assertion interrupt status. t he value of this bit is 1 if the npbin assertion interrupt is triggered. pb 0xc2 6 pbdstat r npbin de-assertion interrupt status. the value of this bit is 1 if the npbin de-assertion interrupt is triggered. pb 0xc2 5 pbastat r npbin status bit. this bit contai ns the real-time status of the npbin pin. the value of this bit is 1 if npbin is asserted, and is 0 if npbin is de-asserted. pb 0xc2 [4:0] - r reserved. pb 0xc3 [7:1] - r reserved. pb 0xc3 0 sipc r/w software initiated power cycle. when this bit is set, the pmu commences a power cycle after 8ms delay. pb 0xc5 [7:2] - r reserved. pb 0xc5 1 pcstat r/w power-cycle flag. the value of this bit is 1 after a power cycle. this bit is automatically cleared to 0 after read. pb 0xc5 0 srstat r/w soft-reset flag. the value of this bit is 1 after a soft-reset. this bit is automatically cleared to 0 after read. gpio6 0xe3 [7] pwm6en r/w pwm function e nable. set 1 to enable pwm function of gpio6. gpio6 0xe3 [6:4] fre6 r/w pwm frequency selection bits for gpio6. see the table 6 for code to frequency cross. gpio6 0xe3 [3:0] duty6 r/w duty cycle selection bits for gpio6. see the table 7 for code to duty cross. gpio5 0xe4 [7] pwm5en r/w pwm function e nable. set 1 to enable pwm function of gpio5. gpio5 0xe4 [6:4] fre5 r/w pwm frequency selection bits for gpio5. see the table 6 for code to frequency cross. gpio5 0xe4 [3:0] duty5 r/w duty cycle selection bits for gpio5. see the table 7 for code to duty cross. gpio3 0xf4 [7] pwm3en r/w pwm function e nable. set 1 to enable pwm function of gpio3. gpio3 0xf4 [6:4] fre3 r/w pwm frequency selection bits for gpio3. see the table 6 for code to frequency cross. gpio3 0xf4 [3:0] duty3 r/w duty cycle selection bits for gpio3. see the table 7 for code to duty cross. gpio4 0xf5 [7] pwm4en r/w pwm function e nable. set 1 to enable pwm function of gpio4. gpio4 0xf5 [6:4] fre4 r/w pwm frequency selection bits for gpio4. see the table 6 for code to frequency cross. gpio4 0xf5 [3:0] duty4 r/w duty cycle selection bits for gpio4. see the table 7 for code to duty cross.
act8848 rev 2, 15-nov-12 innovative power tm - 16 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. system control electr ical characteristics (v inl2 = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit input voltage range 3.0 5.5 v uvlo threshold voltage v inl2 rising 2.6 2.8 3.0 v uvlo hysteresis v inl2 hysteresis 200 mv operating supply current all regulator s enabled but no load 0.6 1.2 ma shutdown supply current all regulators disabled except reg13 10 20 a oscillator frequency 2.0 2.25 2.5 mhz logic high input voltage 1.4 v logic low input voltage 0.4 v low level output voltage nirq, nrsto, isink = 5ma 0.3 v thermal shutdown temperature temperature rising 160 c thermal shutdown hysteresis 20 c leakage current v[nirq] = v[nrsto] = 4.2v 1 a
act8848 rev 2, 15-nov-12 innovative power tm - 17 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. step-down dc/dc electrical characteristics (v vp1 = v vp2 = v vp3 = v vp4 = 3.6v, t a = 25c, unless otherwise specified.) parameter conditions min typ max unit operating voltage range 2.7 5.5 v uvlo threshold input volt age rising 2.5 2.6 2.7 v uvlo hysteresis input voltage falling 100 mv standby supply current v out = 103%, regulator enabled 72 100 a shutdown current v vp = 5.5v, regulator disabled 0 2 a v out 1.0v, i out = 10ma -1% v nom c 1% v v out < 1.0v, i out = 10ma -10 10 mv line regulation v vp = max (v nom 1 +1v, 3.2v) to 5.5v 0.15 %/v load regulation reg2/3 i out = 10ma to imax 2 1.00 %/a power good threshold v out rising 93 %v nom power good hysteresis v out falling 2 %v nom switching frequency v out 20% of v nom 2 2.25 2.5 mhz v out = 0v 550 khz soft-start period 400 s minimum on-time 75 ns reg1 and reg4 maximum output current 1.5 a current limit 1.8 2.2 2.7 a pmos on-resistance i sw = -100ma 0.11 ? nmos on-resistance i sw = 100ma 0.08 ? sw leakage current v vp = 5.5v, v sw = 0 or 5.5v 0 2 a input capacitor 4.7 f output capacitor 33 f power inductor 1.0 2.2 3.3 h reg2 and reg3 maximum output current 2.8 a current limit 3.5 4.2 a pmos on-resistance i sw = -100ma 0.07 ? nmos on-resistance i sw = 100ma 0.08 ? sw leakage current v vp = 5.5v, v sw = 0 or 5.5v 0 2 a input capacitor 10 f output capacitor 44 f power inductor 0.5 1 2.2 h output voltage accuracy load regulation reg1/4 i out = 10ma to imax 2 1.70 %/a c : v nom refers to the nominal output voltage level for v out as defined by the ordering information section. 2 : imax maximum output current.
act8848 rev 2, 15-nov-12 innovative power tm - 18 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. low-noise ldo electri cal characteristics (v inl1 = v inl2 = 3.6v, c out5 = c out6 = c out7 = c out8 = c out9 = 2.2f, t a = 25c, unless otherwise specified.) c : v nom refers to the nominal output voltage level for v out as defined by the ordering information section. 2 : imax maximum output current. 3 : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below the regulation voltage (for 3.1v output voltage or higher). f : ldo current limit is defined as the output current at which th e output voltage drops to 95% of the respective regulation volt age. under heavy overload conditions the output current limit folds back by 50% (typ.) parameter test conditions min typ max unit operating voltage range 2.5 5.5 v output voltage accuracy v out 1.0v, i out = 10ma -1 v nom c 1 % v out < 1.0v, i out = 10ma -10 10 mv line regulation v inl = max (v out + 0.5v, 3.6v) to 5.5v 0.5 mv load regulation i out = 1ma to imax 2 0.1 v/a power supply rejection ratio f = 1khz, i out = 20ma, v out = 1.2v 75 db f = 10khz, i out = 20ma, v out = 1.2v 65 supply current per output regulator enabled 25 a regulator disabled 0 2 soft-start period v out = 3.0v 140 s power good threshold v out rising 92 % power good hysteresis v out falling 3.5 % output noise i out = 20ma, f = 10hz to 100khz, v out = 1.2v 30 v rms discharge resistance ldo disabled, dis[ ] = 1 1.5 k ? ldo rated at 350ma (reg5, reg6, reg7, reg8 & reg9) dropout voltage e i out = 160ma, v out > 3.1v 140 280 mv maximum output current 350 ma current limit f v out = 95% of regulation voltage 400 ma recommend output capacitor 2.2 f
act8848 rev 2, 15-nov-12 innovative power tm - 19 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. low-input voltage ldo elec trical characteristics (v inl3 = 3.6v, c out10 = c out11 = c out12 = 2.2f, t a = 25c, unless otherwise specified.) c : v nom refers to the nominal output voltage level for v out as defined by the ordering information section. 2 : imax maximum output current. 3 : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below the regulation voltage (for 3.1v output voltage or higher). f : ldo current limit is defined as the output current at which th e output voltage drops to 95% of the respective regulation volt age. under heavy overload conditions the output current limit folds back by 50% (typ) parameter test conditions min typ max unit operating voltage range 1.7 5.5 v output voltage accuracy v out 1.0v, i out = 10ma -1 v nom c 1 % v out < 1.0v, i out = 10ma -10 10 mv line regulation v inl = max (v out + 0.5v, 3.6v) to 5.5v 0.5 mv load regulation i out = 1ma to imax 2 0.1 v/a power supply rejection ratio f = 1khz, i out = 20ma, v out = 1.2v 50 db f = 10khz, i out = 20ma, v out = 1.2v 40 supply current per output regulator enabled 22 a regulator disabled 0 2 soft-start period v out = 3.0v 100 s power good threshold v out rising 92 % power good hysteresis v out falling 3.5 % output noise i out = 20ma, f = 10hz to 100khz, v out = 1.2v 30 v rms discharge resistance ldo disabled, dis[ ] = 1 1.5 k ? ldo rated at 350ma (reg10, reg11 & reg12) dropout voltage e i out = 160ma, v out > 3.1v 100 200 mv maximum output current 350 ma current limit f v out = 95% of regulation voltage 400 ma recommend output capacitor 2.2 f
act8848 rev 2, 15-nov-12 innovative power tm - 20 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. low-power(always-on) ldo el ectrical characteristics c : v nom refers to the nominal output voltage level for v out as defined by the ordering information section. (v inl1 = 3.6v, c out13 = 1f, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit reg13 operating voltage range 2.5 5.5 v output voltage accuracy -3 v nom c 3 % line regulation v inl1 = max (v out + 0.2v, 2.5v) to 5.5v 13 mv supply current from v inl1 5 a maximum output current 50 ma recommend output capacitor 0.47 f pwm led driver electric al characteristics (v inl2 = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit output current 100% duty cycle 6 10 16 ma output low voltage feed in with 6ma 0.35 v leakage current sinking from 5.5v source 1 a pwm frequency fre[2:0] = 000 0.25 hz pwm duty adjustment duty[3:0] = 0000 to 1111 6.25 100 %
act8848 rev 2, 15-nov-12 innovative power tm - 21 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. typical performanc e characteristics (t a = 25c, unless otherwise specified.) startup of vin/out13 startup shutdown of npbin/out2/out3/ out1/nrsto/pwrhld startup of npbin/out2/out11/out3/ out1/out4 startup of npbin/out2/out5/out6/ out10/out12 temperature (c) -40 -20 0 20 40 60 80 100 140 120 act8848-001 v ref vs. temperature v ref (v) 1.200 1.196 1.192 1.188 1.184 1.204 act8848-002 frequency vs. temperature frequency (mhz) 2.320 2.300 2.280 2.260 2.240 2.220 2.200 2.180 2.340 2.360 temperature (c) -40 -20 0 20 40 60 80 100 140 120 ch1 ch2 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch4 act8848-003 act8848-004 act8848-005 act8848-006 ch1: v npbin , 2v/div ch2: v out2 , 2v/div ch3: v out3 , 2v/div ch4: v out1, 2v/div ch5: v nrsto, 2v/div ch6: v pwrhld, 5v/div time: 20ms/div ch1: v in , 2v/div ch2: v out13 , 2v/div time: 1ms/div ch1: v npbin , 2v/div ch2: v out2 , 2v/div ch3: v out11 , 2v/div ch4: v out3, 1v/div ch5: v out1, 2v/div ch6: v out4, 5v/div time: 10ms/div ch5 ch6 ch5 ch6 ch5 ch6 ch1: v npbin , 2v/div ch2: v out2 , 1v/div ch3: v out5 , 2v/div ch4: v out6, 5v/div ch5: v out10, 2v/div ch6: v out12, 2v/div time: 10ms/div
act8848 rev 2, 15-nov-12 innovative power tm - 22 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. typical performance ch aracteristics cont?d (t a = 25c, unless otherwise specified.) startup shutdown of out2/out11/ out3/out1 startup shutdown of out2/out4/out5/ out6/out10/out12 startup shutdown of pwren/out7/ out8/out9 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch1 ch2 ch3 ch4 act8848-008 act8848-007 act8848-009 ch1: v out2 , 1v/div ch2: v out11 , 2v/div ch3: v out3 , 1v/div ch4: v out1, 1v/div time: 4ms/div ch1: v pwren , 2v/div ch2: v out7 , 2v/div ch3: v out8 , 2v/div ch3: v out9 , 1v/div time: 1ms/div ch4 ch5 ch6 ch1: v out2 , 2v/div ch2: v out4 , 5v/div ch3: v out5 , 5v/div ch4: v out6, 5v/div ch5: v out10, 2v/div ch6: v out12, 2v/div time: 4ms/div ch1 ch2 ch1: v npbin , 2v/div ch2: v npbstat , 2v/div time: 10ms/div act8848-010 npbin and npbstat
act8848 rev 2, 15-nov-12 innovative power tm - 23 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. typical performance ch aracteristics cont?d (t a = 25c, unless otherwise specified.) reg1 efficiency vs. output current v in = 3.6v v in = 4.0v v in = 5.0v v out = 1.2v 100 80 60 40 20 0 efficiency (%) output current (ma) 0 1 10 10000 1000 100 act8848-011 reg2 efficiency vs. output current output current (ma) 0 1 10 10000 1000 100 efficiency (%) v out = 1.2v v in = 3.6v v in = 4.0v v in = 5.0v act8848-012 reg3 efficiency vs. output current output current (ma) 0 1 10 10000 1000 100 100 80 60 40 20 0 efficiency (%) v out = 1.1v v in = 3.6v v in = 4.0v v in = 5.0v act8848-013 reg4 efficiency vs. output current 100 80 60 40 20 0 efficiency (%) output current (ma) 0 1 10 10000 1000 100 v out = 1.1v v in = 3.6v v in = 4.0v v in = 5.0v act8848-014 100 80 60 40 20 0
act8848 rev 2, 15-nov-12 innovative power tm - 24 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. typical performance ch aracteristics cont?d (t a = 25c, unless otherwise specified.) reg5/6/7/8 dropout voltage vs. output current output current (ma) 0 50 100 150 200 300 250 350 400 dropout voltage (mv) 400 350 300 250 200 150 100 50 0 act8848-015 output current (ma) 0 50 100 150 200 250 300 350 output voltage (v) 2.860 2.840 2.820 2.800 2.780 2.760 2.740 2.720 2.700 2.880 2.900 act8848-016 reg5 output voltage vs. output current output current (ma) 0 50 100 150 200 250 300 350 output voltage (v) 3.360 3.340 3.320 3.300 3.280 3.260 3.240 3.220 3.200 3.380 3.400 act8848-017 reg6 output voltage vs. output current output current (ma) 0 50 100 150 200 250 300 350 output voltage (v) 3.360 3.340 3.320 3.300 3.280 3.260 3.240 3.220 3.200 3.380 3.400 act8848-018 reg7 output voltage vs. output current output current (ma) 0 50 100 150 200 250 300 350 output voltage (v) 1.86 1.84 1.82 1.8 1.78 1.76 1.74 1.72 1.7 1.88 1.9 act8848-019 reg8 output voltage vs. output current output current (ma) 0 50 100 150 200 250 300 350 output voltage (v) 1.260 1.240 1.220 1.200 1.180 1.160 1.140 1.120 1.100 1.280 1.300 act8848-020 reg9 output voltage vs. output current
act8848 rev 2, 15-nov-12 innovative power tm - 25 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. typical performance ch aracteristics cont?d (t a = 25c, unless otherwise specified.) reg10/11/12 dropout voltage vs. output current dropout voltage (mv) 200 150 100 50 0 250 output current (ma) 0 50 100 150 200 250 300 350 400 act8848-021 reg10 output voltage vs. output current output current (ma) 0 50 100 150 200 250 300 350 output voltage (v) 1.260 1.220 1.180 1.140 1.100 1.300 act8848-022 reg11 output voltage vs. output current output current (ma) 0 50 100 150 200 250 300 350 output voltage (v) 1.860 1.820 1.780 1.740 1.700 1.900 act8848-023 reg12 output voltage vs. output current output current (ma) 0 50 100 150 200 250 300 350 output voltage (v) 1.860 1.820 1.780 1.740 1.700 1.900 act8848-024
act8848 rev 2, 15-nov-12 innovative power tm - 26 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. the act8848 is optimized for the telechips tcc88xx and samsung s5pc210 processors, supporting both the power domains as well as the signal interface. the following paragraphs describe how to design act8848 with the tcc88xx processors. while the act8848 supports many possible configurations for powerin g these processors, one of the most common configurations is detailed in this datasheet. system control information interfacing with the tel echips tcc88xx processors table 1: act8848 and telechips tcc88xx power domains act8848 regulator power domain default voltage max current power up order on/off @ sleep type reg1 pwrmem (ddr3) 1.8v 1.5a 3 pwrhld dc/dc step down reg2 vdd_arm 1.45v 2.8a 1 pwrhld dc/dc step down reg3 vdd_g3d 1.25v 2.8a 2 pwrhld dc/dc step down reg4 vdd_int 3.3v 1.5a 3 pwrhld dc/dc step down reg5 vdd_pll 2.8v 350ma 3 pwrhld low-noise ldo reg6 vdd_alive 3.3v 350ma 3 pwrhld low-noise ldo reg7 vdd33_slp_on 3.3v 350ma off pwren low-noise ldo reg8 vdd18_slp_off 1.8v 350ma off pwren low-noise ldo reg9 vdd33_slp_off 1.2v 350ma off pwren low-noise ldo reg10 vdd12_slp_off 1.2v 350ma 3 pwrhld low input-voltage ldo reg11 vdd11_slp_off 1.8v 350ma 1 pwrhld low input-voltage ldo reg12 vdd18_slp_on 1.8v 350ma 3 pwrhld low input-voltage ldo reg13 vdd_rtc 3.3v 50ma 0 n/a always-on ldo
act8848 rev 2, 15-nov-12 innovative power tm - 27 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. control signals enable inputs the act8848 features a variety of control inputs, which are used to enable and disable outputs depending upon the desired mode of operation. pwren, pwrhld are logic inputs, while npbin is a unique, multi-function input. npbin multi-function input the act8848 features the npbin multi-function pin, which combines syst em enable/disable control with a hardware reset function. select either of the two pin functions by asserting this pin, either through a direct connection to ga, or through a 50k ? resistor to ga, as shown in figure 2. manual reset function the second major function of the npbin input is to provide a manual-reset input for the processor. to manually-reset the processor, drive npbin directly to ga through a low impedance (less than 2.5k ? ). an internal timer detects the duration of the mr event: short press / soft-reset: if the mr is asserted for less than 4s, act8848 commences a soft-reset operation where nrsto immediately asserts low, then remains asserted low until the npbin input is de-asserted and the reset time-out period expires. a status bit, srstat[ ] , is set after a soft-reset event. the srstat[ ] bit is automatically cleared to 0 after read. after short press, set wdsren[ ] to 1 about 1s after nrsto de-assert then clear wdsren[ ] for properly shutdown sequence. long press / power-cycle: if the mr is asserted for more than 4s, act8848 commences a power cycle routine in which case all regulators are turned off and then turned back on. a status bit, pcstat[ ], is set after the power cycle. the pcstat[ ] bit is automatically cleared to 0 after read. npbstat output npbstat is an open-drain output that reflects the state of the npbin input; npbstat is asserted low whenever npbin is asserted, and is high-z otherwise. this output is typically used as an interrupt signal to the processor, to initiate a software-programmable routine such as operating mode selection or to open a menu. connect npbstat to an appropriate supply voltage through a 10k ? or greater resistor. figure 2: npbin input nrsto output nrsto is an open-drain output which asserts low upon startup or when manual reset is asserted via the npbin input. when asserted on startup, nrsto remains low until reset time-out period expires. when asserted due to manual-reset, nrsto immediately asserts low, then remains asserted low until the npbin input is de-asserted and the reset time-out period expires. connect a 10k ? or greater pull-up resistor from nrsto to an appropriate voltage supply. nirq output nirq is an open-drain out put that asserts low any time an interrupt is generated. connect a 10k ? or greater pull-up resistor from nirq to an appropriate voltage supply. nirq is typi cally used to drive the interrupt input of the system processor. many of the act8848's f unctions support interrupt- generation as a result of various conditions. these are typically masked by default, but may be unmasked via the i 2 c interface. for more information about the available fault conditions, refer to the appropriate sections of this datasheet.
act8848 rev 2, 15-nov-12 innovative power tm - 28 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. push-button control the act8848 is designed to initiate a system enable sequence when the npbin multi-function input is asserted. once this occurs, a power-on sequence commences, as described below. the power-on sequence must complete and the microprocessor must take control (by asserting pwrhld) before npbin is de-asserted. if the microprocessor is unable to complete its power-up routine successfully before the user releases the push-button, the act8848 automatically shuts the system down. this provides protection against accidental or momentary assertions of the push- button. if desired, longer ?push-and-hold? times can be implemented by simply adding an additional time delay before asserting pwren or pwrhld. control sequences the act8848 features a variety of control sequences that are optimiz ed for supporting system enable and disable. enabling/disabling sequence a typical enable sequence is initiated whenever the npbin is asserted low via 50k ? resistance. the power control diagram is s hown in figure 3. during the boot sequence, the microprocessor must assert pwrhld, and pwren, to ensure that the system remains powered after npbin is released. once the power-up routine is comple ted, the system remains enabled after the push-button is released as long as pwrhld is asserted high. if the processor does not assert pwrhld before the user releases the push-button, the boot-up sequence is terminated and all regulators are disabled. this provides protection against "false-enable", when the push- button is accidentally depressed, and also ensures that the system remains enabled only if the processor successfully completes the boot-up sequence. as with the enable sequence, a typical disable sequence is initiated when the user presses the push-button, which interrupts the processor via the npbstat output. the actual disable sequence is completely software-controlled, but typically involved initiating various ?clean-up? processes before the processor finally de-asserts pwrhld. watch-dog supervision the act8848 features a watchdog supervisory function. an internal watchdog timer of 4s is unmasked by setting either wdsren[ ] or wdpcen [ ] bit to one. once enabled, the watchdog timer is reset whenever there is i 2 c activity for the pmu. in the case where the system software stops responding and that there is no i 2 c transactions for 4s, the watchdog timer expires. as a result, the pmu either perform a soft-reset or power cycle, depending on whether wdsren [ ] or wdpcen [ ] is set. software-initiated power cycle act8848 supports software-initiated power cycle. once the sipc[ ] bit is set, the pmu waits for 8ms and then initiate a power cycle to restart the entire system.
act8848 rev 2, 15-nov-12 innovative power tm - 29 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. figure 3: power control sequence
act8848 rev 2, 15-nov-12 innovative power tm - 30 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. i 2 c interface the act8848 features an i 2 c interface that allows advanced programming capability to enhance overall system performance. to ensure compatibility with a wide range of system processors, the i 2 c interface supports clock speeds of up to 400khz (?fast-mode? operation) and uses standard i 2 c commands. i 2 c write-byte commands are used to program the act8848, and i 2 c read-byte commands are used to read the act8848?s internal registers. the act8848 always operates as a slave device, and is addressed using a 7-bit slave address followed by an eighth bit, which indicates whether the transaction is a read- operation or a write-operation, [1011010x]. sda is a bi-directional data line and scl is a clock input. the master device initiates a transaction by issuing a start condition, defined by sda transitioning from high to low while scl is high. data is transferred in 8-bit packets, beginning with the msb, and is clocked-in on the rising edge of scl. each packet of data is followed by an ?acknowledge? (ack) bit, used to confirm that the data was transmitted successfully. for more information regarding the i 2 c 2-wire serial interface, go to the nxp website: http://www.nxp.com. housekeeping functions programmable battery voltage monitor the act8848 features a programmable battery- voltage monitor, which monitors the voltage at inl2 (which should be connected directly to the battery) and compares it to a programmable threshold voltage. the vbatmon comparator is designed to be immune to noise resulting from switching, load transients, etc. the batmon comparator is disable by default; to enable it, set the batlev[3:0] register to one of the value in table 2. note that there is a 200mv hysteresis between the rising and falling threshold for the comparator. the vbatdat [ - ] bit reflects the output of the batmon comparator. the value of vbatdat[ ] is 1 when v inl2 < batlev; value is 0 otherwise. the vbatmon comparator can generate an interrupt when v inl2 is lower than batlev[ ] voltage. the interrupt is masked by default by can be unmasked by setting vbatmsk[ ] = 1. table 2: batlev falling threshold thermal protection the act8848 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. thermal interrupt if the thermal interrupt is unmasked (by setting ntmsk[ ] to 1), act8848 can generate an interrupt when the die temperature reaches 120c (typ.). thermal protection if the act8848 die temperature exceeds 160c, the thermal protection circuitry disables all regulators and prevents the regulators from being enabled until the ic temperature drops by 20c (typ.). functional description batlev[3:0] batlev falling threshold 0000 2.5 0001 2.6 0010 2.7 0011 2.8 0100 2.9 0101 3.0 0110 3.1 0111 3.2 1000 3.3 1001 3.4 1010 3.5 1011 3.6 1100 3.7 1101 3.8 1110 3.9 1111 4.0
act8848 rev 2, 15-nov-12 innovative power tm - 31 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. general description reg1, reg2, reg3, and reg4 are fixed-frequency, current-mode, synchronous pwm step-down converters that achieves peak efficiencies of up to 97%. these regulators operate with a fixed frequency of 2.25mhz, minimizing noise in sensitive applications and allowing the use of small external components. additionally, reg1, reg2, reg3, and reg4 are available with a variety of standard and custom output voltages, and may be software- controlled via the i 2 c interface for systems that require advanced power management functions. 100% duty cycle operation reg1, reg2, reg3, and reg4 are capable of operating at up to 100% duty cycle. during 100% duty cycle operation, the high-side power mosfets are held on continuously, providing a direct connection from the input to the output (through the inductor), ensuring the lowest possible dropout voltage in battery powered applications. operating mode by default, reg1, reg2, reg3, and reg4 operate in fixed-frequency pwm mode at medium to heavy loads, then transition to a proprietary power-saving mode at light loads in order to save power. synchronous rectification reg1, reg2, reg3, and reg4 each feature integrated synchronous rectifiers, maximizing efficiency and minimizing the total solution size and cost by eliminating the need for external rectifiers. soft-start reg1, reg2, reg3, and reg4 include internal 400 us soft-start ramps which limit the rate of change of the output voltage, minimizing input inrush current and ensuring that the output powers up in a monotonic manner that is independent of loading on the outputs. this circuitry is effective any time the regulator is enabled, as well as after responding to a short-circuit or other fault condition. compensation reg1, reg2, reg3, and reg4 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. no compensation design is required; simply follow a few simple guide lines described below when choosing external components. input capacitor selection the input capacitor reduces peak currents and noise induced upon the voltage source. a 10 f ceramic capacitor is recommended for each regulator in most applications. output capacitor selection reg1, reg2, reg3, and reg4 were designed to take advantage of the benefits of ceramic capacitors, namely small size and very-low esr. reg1, reg2, reg3 and reg4 are designed to operate with 33uf or 44uf output capacitor over most of their output voltage ranges, although more capacitance may be desired depending on the duty cycle and load step requirements. two of the most common dielectrics are y5v and x5r. whereas y5v dielectrics are inexpensive and can provide high capacitance in small packages, their capacitance varies greatly over their voltage and temperature ranges and are not recommended for dc/dc applications. x5r and x7r dielectrics are more suitable for output capacitor applications, as their characteristics are more stable over their operating ranges, and are highly recommended. inductor selection reg1, reg2, reg3, and reg4 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. these devices were optimized for operation with 2.2 h or 1 h inductors. choose an inductor with a low dc- resistance, and avoid inductor saturation by choosing inductors with dc ratings that exceed the maximum output current by at least 30%. configuration options output voltage programming by default, each regulator powers up and regulates to its default output voltage. for reg2, reg3 and reg4, the output voltage is selectable by setting corresponding vsel pin t hat when vsel is low, output voltage is programmed by vset0[ - ] bits, and when vsel is high, output voltage is programmed by vset1[ - ] bits. also, once the system is enabled, each regulator's output voltage may be independently programmed to a different value. program the output voltages via the i 2 c serial interface by writing to the regulator's vset0[ - ] register if vsel is low or vset1[ - ] register if vsel is high as shown in table 3. step-down dc/dc regulators
act8848 rev 2, 15-nov-12 innovative power tm - 32 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. enable / disable control during normal operation, each buck may be enabled or disabled via the i 2 c interface by writing to that regulator's on[ ] bit. ok[ ] and output fault interrupt each dc/dc features a power-ok status bit that can be read by the system microprocessor via the i 2 c interface. if an output voltage is lower than the power- ok threshold, typically 7% below the programmed regulation voltage, that regulator's ok[ ] bit will be 0. if a dc/dc's nfltmsk[ - ] bit is set to 1, the act8848 will interrupt the processor if that dc/dc's output voltage falls below the power-ok threshold. in this case, nirq will assert low and remain asserted until either the regulator is turned off or back in regulation, and the ok[ ] bit has been read via i 2 c. pcb layout considerations high switching frequencies and large peak currents make pc board layout an important part of step-down dc/dc converter design. a good design minimizes excessive emi on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. step-down dc/dcs exhibit discontinuous input current, so the input capacitors should be placed as close as possible to the ic, and avoiding the use of via if possible. the inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. the ground nodes for each regulator's power loop should be connected at a single point in a star- ground configuration, and this point should be connected to the backside ground plane with multiple via. the output node for each regulator should be connected to its corresponding outx pin through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. finally, the exposed pad should be directly connected to the backside ground plane using multiple via to achieve low electrical and thermal resistance. regx/vset[2:0] 000 001 010 011 100 101 110 111 000 0.600 0.800 1.000 1.200 1.600 2.000 2.400 3.200 001 0.625 0.825 1.025 1.250 1.650 2.050 2.500 3.300 010 0.650 0.850 1.050 1.300 1.700 2.100 2.600 3.400 011 0.675 0.875 1.075 1.350 1.750 2.150 2.700 3.500 100 0.700 0.900 1.100 1.400 1.800 2.200 2.800 3.600 101 0.725 0.925 1.125 1.450 1.850 2.250 2.900 3.700 110 0.750 0.950 1.150 1.500 1.900 2.300 3.000 3.800 111 0.775 0.975 1.175 1.550 1.950 2.350 3.100 3.900 regx/vset[5:3] table 3: regx/vset[ ] output voltage setting
act8848 rev 2, 15-nov-12 innovative power tm - 33 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. low-noise, low-dropou t linear regulators general description act8848 features eight low-noise, low-dropout linear regulators (ldos) that supply up to 350ma. three of these ldos (reg10, reg11, and reg12) supports extended input voltage range down to 1.7v. each ldo has been optimized to achieve low noise and high-psrr. output current limit each ldo contains current-limit circuitry featuring a current-limit fold-back function. during normal and moderate overload conditions, the regulators can support more than their rated output currents. during extreme overload conditions, however, the current limit is reduced by approximately 30%, reducing power dissipation within the ic. compensation the ldos are internally compensated and require very little design effort, simply select input and output capacitors according to the guidelines below. input capacitor selection each ldo requires a small ceramic input capacitor to supply current to suppo rt fast transients at the input of the ldo. bypassing each inl pin to ga with 1 f. high quality ceramic capacitors such as x7r and x5r dielectric types are strongly recommended. output capacitor selection each ldo requires a small 2.2 f ceramic output capacitor for stability . fo r best performance, each output capacitor should be connected directly between the output and ga pins, as close to the output as possible, and with a short, direct connection. high quality ceramic capacitors such as x7r and x5r dielectric types are strongly recommended. configuration options output voltage programming by default, each ldo powers up and regulates to its default output voltage. once the system is enabled, each output voltage may be independently programmed to a different value by writing to the regulator's vset[ - ] register via the i 2 c serial interface as shown in table 3. enable / disable control during normal operation, each ldo may be enabled or disabled via the i 2 c interface by writing to that ldo's on[ ] bit. output discharge each of the ldos features an optional output discharge function, which discharges the output to ground through a 1.5k ? resistance when the ldo is disabled. this feature may be enabled or disabled by setting dis[ - ]; set dis[ - ] to 1 to enable this function, clear dis[ - ] to 0 to disable it. ok[ ] and output fault interrupt each ldo features a power-ok status bit that can be read by the system mi croprocessor via the interface. if an output voltage is lower than the power-ok threshold, typically 11% below the programmed regulation voltage, the value of that regulator's ok[ - ] bit will be 0. if a ldo's nfltmsk[ - ] bit is set to 1, the act8848 will interrupt the processor if that ldo's output voltage falls below the power-ok threshold. in this case, nirq will assert low and remain asserted until either the regulator is turned off or back in regulation, and the ok[ - ] bit has been read via i 2 c. pcb layout considerations the act8848?s ldos provide good dc, ac, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. when designing a pcb, however, careful layout is necessary to prevent other circuitry from degrading ldo performance. a good design places input and output capacitors as close to the ldo inputs and output as possible, and utilizes a star-ground configuration for all regulators to prevent noise-coupling through ground. output traces should be routed to avoid close proximity to noisy nodes, particularly the sw nodes of the dc/dcs. refbp is a noise-filtered reference, and internally has a direct connection to the linear regulator controller. any noise injected onto refbp will directly affect the outputs of the linear regulators, and therefore special care should be taken to ensure that no noise is injected to the outputs via refbp. as with the ld o output capacitors, the refbp bypass capacitor should be placed as close to the ic as possible, with short, direct connections to the star-ground. avoid the use of via whenever possible. noisy nodes, such as from the dc/dcs, should be routed as far away from refbp as possible.
act8848 rev 2, 15-nov-12 innovative power tm - 34 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. general description reg13 is an always-on, low-dropout linear regulator (ldo) that is optimized for rtc and backup-battery applications. reg13 features low- quiescent supply current, current-limit protection, and reverse-current protection, and is ideally suited for always-on power supply applications, such as for a real-time clock, or as a backup-battery or super-cap charger. reverse-current protection reg13 features internal circuitry that limits the reverse supply current to less than 1a when the input voltage falls below the output voltage, as can be encountered in backup-battery charging applications. reg13's internal circuitry monitors the input and the output, and disconnects internal circuitry and parasitic diodes when the input voltage falls below the output voltage, greatly minimizing backup battery discharge. typical application voltage regulators reg13 is ideally suited for always-on voltage- regulation applications, such as for real-time clock and memory keep-alive applications. this regulator requires only a small ceramic capacitor with a minimum capacitance of 0.47 f for stability. for best performance, the output capacitor should be connected directly between the output and ga, with a short and direct connection. figure 4: typical application of rtc ldo backup battery charging reg13 features a constant current-limit, which protects the ic under output short-circuit conditions as well as provides a constant charge current, when operating as a backup battery charger. always-on ldo (reg13)
act8848 rev 2, 15-nov-12 innovative power tm - 35 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. the gpio3, the gpio4, the gpio5, and the gpio6 are configured as pwm le d drivers, which could support up to 6ma current with programmable frequency and duty cycle. set pwmxen[ ] bit to ?1? to enable pwm function of gpiox. pwm frequence selection each led driver may be independently programmed to a different frequency by writing to the gpio?s fre[2:0] register via the i 2 c serial interface as shown in table 4. table 4: gpiox/fre[ ] pwm frequency setting pwm duty cycle selection each led driver may be independently programmed to a different duty cycle by writing to the gpio?s duty[3:0] register via the i 2 c serial interface as shown in table 5. table 5: gpiox/duty[ ] pwm frequency setting pwm led drivers gpiox/fre[2:0] pwm frequency [hz] 000 0.25 001 0.5 010 1 011 2 100 128 101 256 gpiox/duty[3:0] pwm duty cycle [%] 0000 6.25 0001 12.5 0010 18.75 0011 25 0100 31.25 0101 37.5 0110 43.75 0111 50 1000 56.25 1001 62.5 1010 68.75 1011 75 1100 81.25 1101 87.5 1110 93.75 1111 100
act8848 rev 2, 15-nov-12 innovative power tm - 36 - www.active-semi.com copyright ? 2012 active-semi, inc. active-semi proprietary D for authorized recipients and customers activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. tqfn66-48 package outline and dimensions symbol dimension in millimeters dimension in inches min max min max a 0.700 0.800 0.032 0.036 a1 0.200 ref 0.008 ref b 0.150 0.250 0.006 0.010 d 6.00 0.24 e 6.00 d2 4.15 4.40 0.166 0.176 e2 4.15 4.40 0.166 0.176 e 0.400 bsc 0.016 bsc l 0.300 0.500 0.012 0.020 r 0.300 0.012 0.24 active-semi, inc. reserves the right to modify the circuitry or specifications without notice. user s should evaluate each product to make sure that it is suitable for their applicat ions. active-semi products are not intended or authorized for use as critical components in life-support dev ices or systems. active-semi, inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. active-semi and its logo are trademarks of active-semi, inc. for more information on this and other products, contact sales@active-semi.com or visit http://www.active-semi.com . is a registered trademark of active-semi.
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